The H5AN4G8NAFR-xxC, H5AN4G8NAFR-xxI, H5AN4G6NAFR-xxC and H5AN4G6NAFR-xxI are a 4Gb CMOS Double Data Rate IV (DDR4) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. SK hynix 4Gb DDR4 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and
8-bit prefetched to achieve very high bandwidth.


• VDD=VDDQ=1.2V +/- 0.06V
• Fully differential clock inputs (CK, CK) operation
• Differential Data Strobe (DQS, DQS)
• On chip DLL align DQ, DQS and DQS transition with CK transition
• DM masks write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
• Programmable CAS latency 9, 11, 12, 13, 14, 15, 16, 17, 18, 19 and 20
• Programmable additive latency 0, CL-1, and CL-2 supported (x4/x8 only)
• Programmable CAS Write latency (CWL) = 9, 10, 11, 12, 14, 16, 18
• Programmable burst length 4/8 with both nibble sequential and interleave mode
• BL switch on the fly
• 16banks
• Average Refresh Cycle (Tcase of 0 oC~ 95 oC) - 7.8 μs at 0oC ~ 85 oC - 3.9 μs at 85oC ~ 95 oC
• JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16)
• Driver strength selected by MRS
• Dynamic On Die Termination supported
• Two Termination States such as RTT_PARK and RTT_NOM switchable by ODT pin
• Asynchronous RESET pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• 8 bit pre-fetch
• This product in compliance with the RoHS directive.
• Internal Vref DQ level generation is available
• Write CRC is supported at all speed grades
• Maximum Power Saving Mode is supported
• TCAR(Temperature Controlled Auto Refresh) mode is supported
• LP ASR(Low Power Auto Self Refresh) mode is sup-ported
• Fine Granularity Refresh is supported
• Per DRAM Addressability is supported
• Geardown Mode(1/2 rate, 1/4 rate) is supported
• Programable Preamble for read and write is supported
• Self Refresh Abort is supported
• CA parity (Command/Address Parity) mode is sup-ported
• Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or differentbank group accesses are available
• DBI(Data Bus Inversion) is supported(x8/x16)

Technical Data Sheet

Technical Data Sheet Technical Data Sheet의 Part Number, Rev., Update Date, Remark를 나타낸 표 입니다.
Part Number Rev. Update Date Remark
H5AN4G6NAFR 1.5 2017-04-14  -xxC / -xxI

Simulation Model

Simulation Model Simulation Model의 Part Number, Rev., Update Date, Remark를 나타낸 표 입니다.
Part Number Rev. Update Date Remark
IBIS_CT 2.1 2015-08-26  
IBIS_IT 2.1 2015-08-26  
Verilog 1.42 2015-06-09  
HSPICE 1.0 2015-04-15  


SpeedSpeed의 Part Number, Speed를 나타낸 표 입니다.
Part Number Speed
PB 1600 11-11-11
RD 1866 13-13-13
TF 2133 15-15-15
UH 2400 17-17-17
VK 2666 19-19-19